As the technology nodes shrink, in some integrated circuit (IC) designs, there has been a desire to replace the typically polysilicon gate electrode with a metal gate electrode to improve device performance with the decreased feature sizes. One process of forming a metal gate structure is termed “gate last” process in which the final gate structure is fabricated “last” which allows for reduced number of subsequent processes, including high temperature processing, that must be performed after formation of the gate. Additionally, as the dimensions of transistors decrease, the thickness of the gate oxide must be reduced to maintain performance with the decreased gate length. In order to reduce gate leakage, high-dielectric-constant (high-k) gate dielectric layers are also used which allow greater physical thicknesses while maintaining the same effective thickness as would be provided by a thinner layer of the gate oxide used in larger technology nodes.
However, there are challenges to implementing such features and processes in CMOS fabrication. As the gate length and spacing between devices decrease, these problems are exacerbated. For example, in a “gate last” fabrication process, voids may be generated during deposition of an inter-layer dielectric (ILD) layer for gap filling.
FIG. 1 shows a cross-sectional view of a field effect transistor (FET) 100 fabricated by a “gate last” process with a conventional spacer structure 118. The FET 100 can be formed over an active region 103 of the substrate 102 adjacent to isolation regions 104. The FET 100 comprises lightly doped regions 122, source/drain regions 124, and silicide regions 126 formed in the active region 103 of the substrate 102, a gate structure 109 comprising a gate dielectric layer 106 and a dummy gate electrode 108 sequentially formed over the substrate 102, gate spacers 118 comprising sealing layers 112 and silicon oxide layers 116 respectively formed on both sidewalls of the gate structure 109. Additionally, a contact etch stop layer (CESL) 134 and an interlayer dielectric (ILD) layer 136 may also be formed over the substrate 102.
Due to the high aspect ratio of the opening between the gate spacers 118, a void 138 is often formed in the ILD layer 136. The void 138 is problematic in various respects. For example, any void 138 present in the ILD layer 136 can become a receptacle of metals during subsequent processing thereby increasing the likelihood of device instability and/or device failure.
Accordingly, what is needed is an improved device and method of spacer formation.